{"id":17557,"date":"2024-09-12T08:17:39","date_gmt":"2024-09-12T15:17:39","guid":{"rendered":"https:\/\/princessleia.com\/journal\/?p=17557"},"modified":"2024-09-11T15:46:02","modified_gmt":"2024-09-11T22:46:02","slug":"ibm-telum-ii-at-hot-chips","status":"publish","type":"post","link":"https:\/\/princessleia.com\/journal\/2024\/09\/ibm-telum-ii-at-hot-chips\/","title":{"rendered":"IBM Telum II at Hot Chips"},"content":{"rendered":"<p>Back in 2021 the IBM Telum processor, the heart of the IBM z16 mainframe, was unveiled at Hot Chips (<a href=\"https:\/\/www.youtube.com\/watch?v=fUqOdu2ympk\">video here<\/a>). I watched the recording when it came out, absolutely glued to each little detail that was presented, even the ones I didn&#8217;t fully understand (after all, I&#8217;m not <em>that<\/em> much of a processor expert). Over the coming weeks, articles like this one from AnandTech would come out, diving deeper into the cache redesign: <a href=\"https:\/\/www.anandtech.com\/show\/16924\/did-ibm-just-preview-the-future-of-caches\">Did IBM Just Preview The Future of Caches?<\/a> by Dr. Ian Cutress. Very cool stuff.<\/p>\n<p>The truth is, <em>every<\/em> new mainframe has a new chip, and all of them have impressive new features that are innovative and exciting, but this is the first time in a long time that there was such a detailed technical splash with a named chip. What a roll out!<\/p>\n<p>When I learned that Hot Chips would once again be hosted at Stanford, just across the bay from me, I jumped at the opportunity to attend for the next announcement: IBM Telum II<\/p>\n<div align=\"center\"><a href=\"\/images\/journalpics\/092024\/hot_chips_sign.jpg\"><img decoding=\"async\" src=\"\/images\/journalpics\/092024\/hot_chips_sign_sm.jpg\"><\/a><\/div>\n<p>I was a little nervous about the event because of how deeply technical the sessions were on the hardware side, but I quickly found my stride. Since I haven&#8217;t kept up very closely on processor design, it was interesting to learn about Intel&#8217;s Lunar Lake processor, including the work they&#8217;ve done toward power reduction. But I&#8217;d say the general theme of the day was hardware accelerated AI on the processor. Telum II fit right in and Chris Berry gave a great presentation.<\/p>\n<div align=\"center\"><a href=\"\/images\/journalpics\/092024\/hot_chips_telum_ii_presentation_1.jpg\"><img decoding=\"async\" src=\"\/images\/journalpics\/092024\/hot_chips_telum_ii_presentation_1_sm.jpg\"><\/a><\/div>\n<p>Now it&#8217;s time for me to geek out about it. As you can see, some of the big numbers that make this chip distinctive:<\/p>\n<ul>\n<li>A new built-in low-latency data processing unit (DPU) for accelerated IO<\/li>\n<li>8 high-performance cores running at 5.5GHz<\/li>\n<li>40% increase in on-chip cache capacity<\/li>\n<li>A new AI accelerator, the compute power of each accelerator is expected to be improved by 4x over Telum, reaching 24 trillion operations per second (TOPS)<\/li>\n<\/ul>\n<p>See more on the <a href=\"https:\/\/www.ibm.com\/blog\/announcement\/telum-ii\/\">full announcement from IBM<\/a> and on the <a href=\"https:\/\/www.ibm.com\/z\/telum\">IBM Telum page<\/a>.<\/p>\n<div align=\"center\"><a href=\"\/images\/journalpics\/092024\/hot_chips_telum_ii_presentation_2.jpg\"><img decoding=\"async\" src=\"\/images\/journalpics\/092024\/hot_chips_telum_ii_presentation_2_sm.jpg\"><\/a><\/div>\n<p>This time there was a second announcement too, the IBM Spyre Accelerator PCIe attached card. If you&#8217;re at all familiar with mainframes, you know that the PCIe drawers make up a nice chunk of the system, with cards to handle various functions that are separate from the compute drawer, which houses the processors and memory. Having a dedicated AI accelerator card was a logical step forward, so I was really excited to be there for its debut.<\/p>\n<div align=\"center\"><a href=\"\/images\/journalpics\/092024\/hot_chips_spyre_pcie_1.jpg\"><img decoding=\"async\" src=\"\/images\/journalpics\/092024\/hot_chips_spyre_pcie_1_sm.jpg\"><\/a><\/div>\n<p>Again from the announcement linked above, <em>&#8220;The Spyre Accelerator will contain 32 AI accelerator cores that will share a similar architecture to the AI accelerator integrated into the Telum II chip.&#8221;<\/em><\/p>\n<div align=\"center\"><a href=\"\/images\/journalpics\/092024\/hot_chips_spyre_pcie_2.jpg\"><img decoding=\"async\" src=\"\/images\/journalpics\/092024\/hot_chips_spyre_pcie_2_sm.jpg\"><\/a><\/div>\n<p>After the talk, I got to meet up with the other IBMers who were in attendance, which gave me the opportunity to meet Chris <em>and<\/em> Christian, who had spoken at the last Hot Chips.<\/p>\n<div align=\"center\"><a href=\"\/images\/journalpics\/092024\/hot_chips_lyz_christian_chris.jpg\"><img decoding=\"async\" src=\"\/images\/journalpics\/092024\/hot_chips_lyz_christian_chris_sm.jpg\"><\/a><\/div>\n<p>At this event I also got to meet a couple folks from <a href=\"https:\/\/chipsandcheese.com\/\">Chips and Cheese<\/a> who were covering the event, and wrote an article that came out last week, <a href=\"https:\/\/chipsandcheese.com\/2024\/09\/08\/telum-ii-at-hot-chips-2024-mainframe-with-a-unique-caching-strategy\/\">Telum II at Hot Chips 2024: Mainframe with a Unique Caching Strategy<\/a>, which was referenced in a recent Hackaday article <a href=\"https:\/\/hackaday.com\/2024\/09\/08\/mainframe-chip-has-360mb-of-on-chip-cache\/\">Mainframe Chip Has 360MB Of On-Chip Cache<\/a> and led to a few of my non-mainframe friends seeing it.<\/p>\n<p>They also set up <a href=\"https:\/\/chipsandcheese.com\/2024\/09\/05\/an-interview-with-susan-eickoff-and-christian-jacobi-from-ibm-at-hot-chips-2024\/\">an interview with Susan Eickoff and Christian Jacobi<\/a>, during which Susan shared view into development, beginning with how far out they have to plan (5+ years), a lead time that means its predecessor hasn&#8217;t even been released yet. I love these interviews because they give a public view into why certain things were designed in a specific way, which the community doesn&#8217;t often get to hear about from IBM. I wish we did more of these behind-the-scenes things at industry events that are so close to the tech community, there&#8217;s so much fascinating innovation happening at IBM and I <em>still<\/em> run into people who are surprised when they learn about it.<\/p>\n<p>As I made my way around the event, I saw some more fascinating talks, but also got to meet a bunch of people. I spoke to a professor at Stanford and some of his students about open source and hardware architectures. I met Lori Servin of the RISC-V Foundation and got to geek out a bit over the talks I&#8217;ve been giving about porting open source software to various architectures.<\/p>\n<div align=\"center\"><a href=\"\/images\/journalpics\/092024\/hot_chips_lori_risc-v.jpg\"><img decoding=\"async\" src=\"\/images\/journalpics\/092024\/hot_chips_lori_risc-v_sm.jpg\"><\/a><\/div>\n<p>I also got to spend a few minutes with Dr. Ian Cutress, who wrote the article on caches that I read three years ago (linked above).<\/p>\n<div align=\"center\"><a href=\"\/images\/journalpics\/092024\/hot_chips_ian.jpg\"><img decoding=\"async\" src=\"\/images\/journalpics\/092024\/hot_chips_ian_sm.jpg\"><\/a><\/div>\n<p>In all, it was a great event and I&#8217;m grateful that I could attend. The following day I watched the live stream from home to check out what companies like Meta and Tesla are doing, plus a keynote from Victor Peng, President of AMD who spoke on our future of AI pervasiveness. It was a real stretch for me on a technical level, there are things I simply don&#8217;t understand and appreciate about chip design, but what I could follow (or quickly look up) made the event quite the learning experience.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Back in 2021 the IBM Telum processor, the heart of the IBM z16 mainframe, was unveiled at Hot Chips (video here). I watched the recording when it came out, absolutely glued to each little detail that was presented, even the ones I didn&#8217;t fully understand (after all, I&#8217;m not that much of a processor expert). [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[9,43,37,24],"tags":[],"class_list":["post-17557","post","type-post","status-publish","format-standard","hentry","category-events","category-mainframes","category-tech","category-work"],"_links":{"self":[{"href":"https:\/\/princessleia.com\/journal\/wp-json\/wp\/v2\/posts\/17557","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/princessleia.com\/journal\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/princessleia.com\/journal\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/princessleia.com\/journal\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/princessleia.com\/journal\/wp-json\/wp\/v2\/comments?post=17557"}],"version-history":[{"count":9,"href":"https:\/\/princessleia.com\/journal\/wp-json\/wp\/v2\/posts\/17557\/revisions"}],"predecessor-version":[{"id":17566,"href":"https:\/\/princessleia.com\/journal\/wp-json\/wp\/v2\/posts\/17557\/revisions\/17566"}],"wp:attachment":[{"href":"https:\/\/princessleia.com\/journal\/wp-json\/wp\/v2\/media?parent=17557"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/princessleia.com\/journal\/wp-json\/wp\/v2\/categories?post=17557"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/princessleia.com\/journal\/wp-json\/wp\/v2\/tags?post=17557"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}